Analog chip #3 Interface Document.
May 27th 1997.




1    vbp_f                       Reference voltage
2    v_ref                       "
3    vbn_f                       "
4    in_cal_impaire              Odd channels calibration inputs
5    VDD_ana  -  vdd             Analog Voltage supply
6    gain                        Gain control
7    vbp_dif7 -  res + pot - gnd Gain adjust from threshold DAC #7
8    in7                         Input #7
9    GND7     -  gnd
10   vbp_dif6 -  res + pot - gnd Gain adjust from threshold DAC #6
11   in6                         Input #6
12   GND6     -  gnd
13   vbp_dif5 -  res + pot - gnd Gain adjust from threshold DAC #5
14   in5                         Input #5
15   GND5     -  gnd
16   vbp_dif4 -  res + pot - gnd Gain adjust from threshold DAC #4 
17   in4                         Input #4
18   GND4     -  gnd
19   vbp_dif3 -  res + pot - gnd Gain adjust from threshold DAC #3
20   in3                         Input #3
21   GND3     -  gnd
22   vbp_dif2 -  res + pot - gnd Gain adjust from threshold DAC #2
23   in 2                        Input #2
24   GND2        gnd
25   vbp_dif1 -  res + pot - gnd Gain adjust from threshold DAC #1
26   in1                         Input #1
27   GND1        gnd
28   vbp_dif0 -  res + pot - gnd Gain adjust from threshold DAC #0
29   in0                         Input #0
30   GND0        gnd
31   vbn_in
32   VDD_out  -  vdd
33   VDD_in   -  vdd
34   vbn_d
          I      res             Bias current in comparator
35   vbp_d                       "
36   vd       -  res - vdd       
37   vbn_a    -  res - vdd       Bias current in followers
38   i_ecl    -  res - gnd       Bias current in PECL to CMOS Converter
39   select*                     Multiplexer select
40   !select*                    "
41   GND_dig  -  gnd             Digital ground
42   a2                          Multiplexer address PECL
43   a2*                         "
44   VDD_mux  -  vdd
45   out_shaper                  Multiplexer output
46   a1                          Multiplexer address PECL
47   a1*                         "
48   a0                          "
49   a0*                         "
50   out_cfd0                    Discriminator output
51   out_cfd1                    "
52   out_cfd2                    "
53   out_cfd3                    "
54   out_cfd4                    "
55   out_cfd5                    "
56   out_cfd6                    "
57   out_cfd7 
58   VDD_discr - vdd
59   V_source  - gnd
60   VDD_dig   - vdd1            Digital Vdd
61   VDD_dig   - vdd1            "
62   vbp_icon    
             I   res             Bias current in Icon #1 and Icon #2
63   vbn_icon  
64   vbp_aw
             I   res             Bias current in Follower #3 and Follower #4
65   vbn_aw                      "
66   vbp_amp                     Amplifier supply
67   vbn_amp                     "
68   in_cal_paire                Even calibration channels input